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| 1 ? 2001 integrated device technology, inc. time slot interchange digital switch 256 x 256 IDT728985 dsc-5708/2 ? ? ? ? ? 256 x 256 channel non-blocking switch ? ? ? ? ? automatic signal identification (st-bus ? , gci) ? ? ? ? ? 8 rx inputs ? 32 channels at 64 kbit/s per serial line ? ? ? ? ? 8 tx outputs ? 32 channels at 64 kbit/s per serial line ? ? ? ? ? three-state serial outputs ? microprocessor interface (8-bit data bus) ? ? ? ? ? frame integrity for data applications ? ? ? ? ? 5v power supply ? ? ? ? ? operating temperature range -40 c to +85 c ? ? ? ? ? available in 44-pin plastic leaded chip carrier (plcc), 44-pin plastic quad flatpack (pqfp) and 40-pin plastic dip (p-dip) the IDT728985 is a st-bus ? /gci compatible digital switch controlled by a microprocessor. the IDT728985 can handle as many as 256, 64 kbit/s input and output channels. those 256 channels are divided into 8 serial inputs and outputs, each of which consists of 32 channels. the IDT728985 provides per- channel variable or constant throughput delay modes and microprocessor read and write access to individual channels. as an important function of a digital switch is to maintain sequence integrity and minimize throughput delay, the IDT728985 is an ideal solution for most switching needs. frame sequence, constant throughput delay, and guaranteed minimum delay are high priority requirements in today?s integrated data and multimedia networks. the IDT728985 provides these functions on a per-channel basis using a standard microprocessor control interface. each of the eight serial lines is designed to switch 64 kbit/s pcm or n x 64 kbit/s data. in processor mode, the microprocessor can access the input and output time slots to control other devices such as isdn transceivers and trunk interfaces. supporting both gci and st-bus ? formats, IDT728985 has incorporated an internal circuit to automatically identify the polarity and format of the frame synchronization. a functional block diagram of the IDT728985 device is shown on page 1. the serial streams operate continuously at 2.048 mb/s and are arranged in 125 s wide frames each containing 32, 8-bit channels. eight input (rx0-7) and microprocessor interface control register timing unit rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 tx0 tx1 tx2 tx3 tx4 tx5 tx6 tx7 ode f0i c4i v cc cs ds r/ w a0/ a5 gnd cco dta d0/ d7 5708 drw01 receive serial data streams data memory output mux connection memory transmit serial data streams 2 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 35 34 33 32 31 30 29 37 36 3 2 44 1 43 42 41 5 4 6 5708 drw02 index 38 39 40 21 22 24 23 25 26 27 19 20 18 28 ds cs r/ w 11 12 13 14 15 16 17 9 10 8 7 rx2 rx1 rx0 dta tx0 tx1 tx2 dnc (1) cco ode tx3 tx4 tx5 tx6 tx7 gnd d 0 rx3 rx4 rx5 rx6 rx7 v cc f0i c4i a 0 d 1 d 2 d 3 d 4 a 1 a 2 dnc (1) dnc (1) dnc (1) d 5 d 6 d 7 a 5 a 4 a 3 dta cco ode 1 2 40 39 tx0 3 38 tx1 4 37 tx2 5 36 tx3 6 35 tx4 7 34 tx5 8 33 tx6 9 32 tx7 10 31 gnd 11 30 d 0 12 29 cs 13 28 14 27 5708 drw04 15 16 17 18 19 20 26 25 24 23 22 21 rx1 rx2 rx3 rx4 rx5 rx6 f0i a 0 r/ w ds c4i v cc rx7 rx0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 a 1 a 2 a 3 a 4 a 5 plcc: 0.05in. pitch, 0.65in. x 0.65in. (j44-1, order code: j) top view plastic dip: 0.10in. pitch, 2.05in. x 0.60in. (p40-1, order code: p) top view 29 28 27 26 25 24 23 31 30 44 43 42 41 5708 drw03 index 32 33 40 ds cs r/ w 5 6 7 8 9 10 11 3 4 2 1 rx2 rx1 rx0 dta tx0 tx1 tx2 dnc (1) cco ode tx3 tx4 tx5 tx6 tx7 gnd d 0 rx3 rx4 rx5 rx6 rx7 v cc f0i c4i a 0 d 1 d 2 d 3 d 4 a 1 a 2 dnc (1) dnc (1) dnc (1) d 5 d 6 d 7 a 5 a 4 a 3 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 pqfp: 0.80mm pitch, 10mm x 10mm (db44-1, order code: db) top view note: 1. dnc - do not connect symbol name i/o description gnd ground. ground rail. v cc v cc +5.0 volt power supply. dta data acknowledgment o this active low output indicates that a data bus transfer is complete. a pull-up resistor is required at th is (open drain) output. rx0-7 rx input 0 to 7 i serial data input streams. these streams have 32 channels at data rates of 2.048 mb/s. f0i frame pulse i this input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as st-bus ? and gci. c4i clock i 4.096 mhz serial clock for shifting data in and out of the data streams. a0-a5 address 0 to 5 i these lines provide the address to IDT728985 internal registers. ds data strobe i this is the input for the active high data strobe on the microprocessor interface. this input operates with cs to enable the internal read and write generation. r/ w read/write i this input controls the direction of the data bus lines (d0-d7) during a microprocessor access. cs chip select i active low input enabling a microprocessor read or write of control register or internal memories. d0-d7 data bus 0 to 7 i/o these pins provide microprocessor access to data in the internal control register. connection memory high, connection memory low and data memory. tx0-7 tx outputs 0 to 7 o serial data output streams. these streams are composed of 32, 64 kbit/s channels at data rates of 2.048 mb/s. (three-state outputs) ode output drive enable i this is an output enable for the tx0-7 serial outputs. if this input is low, tx0-7 are high-impedance. i f this is high, each channel may still be put into high-impedance by software control. cco control channel output o this output is a 2.048 mb/s line which contains 256 bits per frame. the level of each bit is controll ed by the contents of the cco bit in the connection memory high locations. 3 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 eight output (tx0-7) serial streams are provided in the IDT728985 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. the serial interface clock for the device is 4.096 mhz, as required in st-bus ? and gci specifications. the received serial data is internally converted to parallel by the on chip serial-to-parallel converters and stored sequentially in a 256-position data memory. by using an internal counter that is reset by the input 8 khz frame pulse, f0i, the incoming serial data streams can be framed and sequentially addressed. depending on the type of information to be switched, the IDT728985 device can be programmed to perform time slot interchange functions with different throughput delay capabilities on a per-channel basis. the variable delay mode, most commonly used for voice applications, can be selected ensuring minimum throughput delay between input and output data. in constant delay mode, used in multiple or grouped channel data applications, the integrity of the information through the switch is maintained. connection memory data to be output on the serial streams may come from two sources: data memory or connection memory. the connection memory is split into high and low parts and is associated with particular tx output streams. in processor mode, data output on the tx streams is taken from the connection memory low and originates from the microprocessor (figure 2). where as in connection mode (figure 1), data is read from data memory and originated from the incoming rx streams. data destined for a particular channel on the serial output stream is read internally during the previous channel time slot to allow time for memory access and internal parallel-to-serial conversion. connection mode in connection mode, the addresses of input source for all output channels are stored in the connection memory low. the connection memory low locations are mapped to corresponding 8-bit x 32-channel outputs. the contents of the data memory at the selected address are then transferred to the parallel- to-serial converters before being output. by having the output channel to specify the input channel through the connection memory, the same input channel can be broadcast to several output channels. processor mode in processor mode the cpu writes data to the connection memory low locations which correspond to the output link and channel number. the contents of the connection memory low are transferred to the parallel-to-serial converter one channel before it is to be output and are transmitted each frame to the output until it is changed by the cpu. control the connection memory high bits (table 4) control the per-channel functions available in the IDT728985. output channels are selected into specific modes such as: processor mode or connection mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. there is also one bit to control the state of the cco output pin. output drive enable (ode) the ode pin is the master output three-state control pin. if the ode input is held low all tdm (time division multiplexed) outputs will be placed in high impedance regardless connection memory high programming. however, if ode is high, the contents of connection memory high control the output state on a per-channel basis. serial interface timing the IDT728985 master clock ( c4i ) is 4.096 mhz signal allowing serial data link configuration at 2.048 mb/s to be implemented. the IDT728985 can automatically detect the presence of an input frame pulse, identify the type of backplane present on the serial interface, and format the synchronization pulse according to st-bus ? or gci interface specifications (active high in gci or active low in st-bus ? ). upon determining the correct interface connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. in st-bus ? mode, every second falling edge of the 4.096 mhz clock marks a boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. in gci mode every second rising edge of the 4.096 mhz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries. the transfer of information from the input serial streams to the output serial streams results in a delay through the device. the delay through the IDT728985 device varies according to the mode selected in the v /c bit of the connection memory high. variable delay mode the delay in variable delay mode is dependent only on the combination of source and destination on the input and output streams. the minimum delay achievable in the IDT728985 device is three time slots. in the IDT728985 device, the information that is to be output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). the same occurs if the input channels succeeding (n+1, n+2) the channel position as the information is input. the information switched to the third time slot after the input has entered the device (for instance, input channel 0 to output channel 3 or input channel 30 to output channel 1), is always output three channels later. any switching configuration that provides three or more time slots between input and output channels, will have a throughput delay equal to the difference figure 2. processor mode figure 1. connection mode receive serial data streams 5708 drw05 rx tx transmit serial data streams data memory connection memory 5708 drw06 tx microprocessor receive serial data streams transmit serial data streams data memory connection memory !"#$ 4 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 between the output and input channels; i.e., the throughput delay will be less than one frame. table 1 shows the possible delays for the IDT728985 device in variable delay mode. an example is shown in figure 3. constant delay mode in this mode frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer technique where input channels written in any of the buffers during frame n will be read out during frame n+2. in the IDT728985, the minimum throughput delay achievable in constant delay mode will be 32 time slots; for example, when input time slot 32 (channel 31) is switched to output time slot 1 (channel 0). likewise, the maximum delay is achieved when the first time slot in a frame (channel 0) is switched to the last time slot in the frame (channel 31), resulting in 94 time slots of delay (see figure 4). to summarize, any input time slot from input frame n will be always switched to the destination time slot on output frame n+2. in constant delay mode the device throughput delay is calculated according to the following formula: delay=[32+(32-in)+(out-1)] in =the number of the input time slot (from 1 to 32) out = the number of the output time slot (from 1 to 32). the IDT728985 microprocessor port is a non-multiplexed bus architecture. the parallel port consists of an 8-bit parallel data bus (d0-d7), six address input lines (a0-a5) and four control lines ( cs , ds, r/ w and dta ). this parallel microport allows the access to the control registers, connection memory low, connection memory high, and the data memory. all locations are read/written except for the data memory, which can be read only. accesses from the microport to the connection memory and the data memory are multiplexed with accesses from the input and output tdm ports. this can cause variable data acknowledge delays ( dta ). in the IDT728985 device, the dta output provides a maximum acknowledgment delay of 800ns for read/write operations in the connection memory. however, for operations in the data memory (processor mode), the maximum acknowledgment delay can be 1220ns. % if the a5, a1, a0 address line inputs are low then the IDT728985 internal control register is addressed (see table 2). if a5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. as explained in the control register description, the address input lines and the stream address bits (sta) of the control register give the user the capability of selecting all positions of IDT728985 data and connect memories. see figure 6 for accessing internal memories. the data in the control register consists of memory select and stream address bits, split memory and processor enable bits (table 3). in split memory mode (bit 7 of the control register) reads are from the data memory and writes are to the connection memory low. the memory select bits allow the connection memory high or low or the data memory to be chosen, and the stream address bits define internal memory subsections corresponding to input or output streams. the processor enable bit (bit 6) places every output channel on every output stream in processor mode; i.e., the contents of the connection memory low (cml, table 5) are output on the output streams once every frame unless the ode input pin is low. if pe bit is high, then the IDT728985 behaves as if bits 2 (channel source) and 0 (output enable) of every connection memory high (cmh) locations were set to high, regardless of the actual value. if pe is low, then bit 2 and 0 of each connection memory high location operates normally. in this case, if bit 2 of the cmh is high, the associated tx output channel is in processor mode. if bit 2 of the cmh is low, then the contents of the cml define the source information (stream and channel) of the time slot that is to be switched to an output, table 4. if the ode input pin is low, then all the serial outputs are high-impedance. if ode is high, then bit 0 (output enable) of the cmh location enables (if high) or disables (if low) for that particular channel. the contents of bit 1 (cco) of each connection memory high location (see table 4) is output on cco pin once every frame. the cco pin is a 2.048 mb/s output, which carries 256 bits. if cco bit is set high, the corresponding bit on cco output is transmitted high. if cco is low, the corresponding bit on the cco output is transmitted low. the contents of the 256 cco bits of the cmh are transmitted sequentially on to the cco output pin and are synchronous to the tx streams. to allow for delay in any external control circuitry the contents of the cco bit is output one channel before the corresponding channel on the tx streams. for example, the contents of cco bit in position 0 (corresponding to tx0, ch0), is transmitted synchronously with the tx channel 31, bit 7. bit 1's of cmh for channel 1 of streams 0-7 are output synchronously with tx channel 0 bits 7-0. initialization during the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. care should be taken that no two connected tx outputs drive the bus simultaneously. the ode pin should be held low on power up to keep all output pins in high-impedance. with the cmh setup, the microprocessor controlling the matrices can bring the ode signal high to relinquish high impedance state control to the connection memory high bits outputs. ? a5 a4 a3 a2 a1 a0 location 0 x x x 0 0 control register (1) 100000 channel 0 (2) 100001 channel 1 (2) 1 ????? ? 1 ????? ? 1 ????? ? 1 ????? ? 1 ????? ? 111111 channel 31 (2) ? & input channel output channel throughput delay n m=n, n+1 or n+2 m-n+32 time slot n m>n+2 m-n time slot n m 6 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 connection memory high connection memory low 0 1 1 0 1 1 control register cr b 7 5708 drw08 the control register is only accessed when a5=0. all other address bits have no effect when a5=0. when a5 =1, only 32 bytes are randomly accessable via a0-a4 at any one instant. which 32 bytes are accessed is determined by the state of crb0 -crb4. the 32 bytes correlate to 32 channel of one st-bus ? stream. cr b 6cr b 5cr b 4cr b 3cr b 2cr b 1cr b 0 cr b 4cr b 3 000 0 001 1 01 0 2 011 3 100 4 101 5 110 6 111 7 stream cr b 2cr b 1cr b 0 100001 100010 100000 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 111111 external address bits a5-a0 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 channel 31 data memory figure 6. addressing internal memories 7 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 ' ? ? % ( ? bit name description 7 sm (split memory) when 1, all subsequent reads are from the data memory and writes are to the connection memory, except when the control register is accessed again. the memory select bits need to specify the memory for the operations. 6 pe (processor mode) when 1, the contents of the connection memory low are output on the serial output streams except when in hi gh- impedance. when 0, the connection memory bits for each channel determine what is output. 5 unused 4-3 ms1-ms0 0-0 - not to be used. (memory select bits) 0-1 - data memory (read only from the cpu) 1-0 - connection memory low 1-1 - connection memory is high 2-0 sta2-0 the number expressed in binary notation on these bits refers to the input or output stream which corresponds to the (stream address bits) subsection of memory made accessible for subsequent operations. sm pe x ms1 ms0 sta2 sta1 sta0 76543210 x = don't care x = don't care bit name description 7,5,4,3 unused 6 v /c (variable/constant this bit is used to select between variable (low) and constant delay (high) modes on a per-channel basis. throughput delay mode) 2 cs when 1, the contents of the corresponding location in connection memory low are output on the location's channel (channel source) and stream. when 0, the contents of the corresponding location in connection memory low act as an address for t he data memory and determine the source of the connection to the location's channel and stream. 1 cco (cco bit) this bit drives a bit time on the cco output pin. 0 oe (output enable) this bit enables the output drivers on a per-channel basis. this allows individual channels on individual st reams to be made high-impedance, allowing switch matrices to be constructed. a high enables the driver and a low disables it. x v /cxxxcsccooe 76543210 bit name description 7-5 sab2-0 (1) these three bits are used to select eight source streams for the connection. (source stream address bits) 4-0 (1) cab2-0 (1) these five bits are used to select 32 different source channels for the connection (the stream where the channel (source channel address bits) is present is defined by bits sab2-0). bit 4 is the most significant bit. sab2 sab1 sab0 cab4 cab3 cab2 cab1 cab0 note: 1. if bit 2 of the corresponding connection high location is 1 or bit 6 of the control register is 1, then these entire 8 bits a re output on the channel and stream associated with this location. otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. 76543210 8 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 test point output pin c l gnd s 1 r l vcc gnd 5708 drw09 s 2 s1 is open circuit except when testing output levels or high impedance states. s2 is switched to v cc or gnd when testing output levels or high impedance states. figure 6. output load note: 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. note: 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. symbol parameter min. max. unit v cc - gnd -0.3 7 v vi voltage on digital inputs gnd - 0.3 v cc +0.3 v v o voltage on digital outputs gnd - 0.3 v cc +0.3 v i o current at digital outputs 40 ma t s storage temperature -65 +150 c p d package power dissapation 2 w symbol parameter min. typ. (1) max. unit v cc positive supply 4.75 5.0 5.25 v v i input voltage 0 ? v cc v t op operating temperature -40 25 +85 c commercial symbol parameter min. typ. (1) max. units test conditions i cc supply current ? 7 10 ma outputs unloaded v ih input high voltage 2.0 ?? v v il input low voltage ?? 0.8 v i il input leakage (inputs) ?? 5 av i between gnd and v cc i il input leakage (i/o pins) ? 34 100 a c i input capacitance ? 8 ? pf v oh output high voltage 2.4 ?? vi oh = 10ma i oh output high current 10 15 ? ma sourcing. v oh = 2.4v v ol output low voltage ?? 0.4 v i ol = 5ma i ol output low current 5 10 ? ma sinking. v ol = 0.4v i oz high impedance leakage ?? 5 av o between gnd and v cc c o output pin capacitance ? 8 ? pf note: 1. exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ) $ 9 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 $ ? * + figure 7. st-bus ? timing f0i c4i tx rx 5708 drw 10 ch. 31, bit 0 ch. 0, bit 7 ch. 0, bit 6 ch. 0, bit 6 ch. 0, bit 7 ch. 31, bit 0 ch. 0, bit 5 t f0iw ch. 0, bit 5 t f0ih t f0is t daa t c4i t stis t stih t ch t cl t f t r note: 1. timing is over recommended temperature and power supply voltages (v cc =5v 5%, gnd=0v, ta=40 c to 85 c). 2. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. symbol parameter min. typ. (2) max. units t est conditions t f0iw frame pulse width ? 244 ? ns outputs loaded t f0is frame pulse setup time 10 ? 190 ns t f0ih frame pulse hold time 20 ? 190 ns t daa tx delay active to active ? 40 60 ns c l = 150pf t stis rx setup time 20 ?? ns t stih rx hold time 20 ?? ns t c4i clock period 200 244 300 ns t cl ck input low 85 122 150 ns t ch ck input high 85 122 150 ns t r, t f clock rise/fall time ?? 10 ns 10 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 figure 8. gci timing t daa tx rx 5708 drw11 t stis t stih t wfh f0i c4i t ch t cl t f t r t c4i ch. 31 bit 7 ch. 0 bit 0 ch. 0 bit 1 ch. 0 ch. 0 bit 1 bit 0 ch. 31 bit 7 t f0is t f0ih $ ? note: 1. timing is over recommended temperature and power supply voltages (v cc =5v 5%, gnd=0v, ta=40 c to 85 c). 2. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. symbol parameter min. typ. (2) max. units test conditions t c4i clock period 150 244 300 ns outputs loaded tcl, tch pulse width 73 122 150 ns t wfh frame width high ? 244 ? ns t f0is frame setup 10 ? 190 ns t f0ih frame hold 20 ? 190 ns t daa data delay/clock active to active ? 40 60 ns c l = 150pf t stis serial input setup 20 ?? ns t stih serial input hold 20 ?? ns t r, t f clock rise/fall time ?? 10 ns 11 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 c4i tx0-7 cco 5708 drw12 tx0-7 (gci) (st-bus ? ) bit cell boundary t taz t xcd t tza figure 9. serial outputs and external control figure 10. output driver enable t oed ode tx0-7 5708 drw13 t oed $ ? symbol characteristics min. typ. (2) max. unit test conditions t taz tx0-7 delay - active to high z ? 40 60 ns r l = 1k ? (3) , c l = 150pf t tza tx0-7 delay - high z to active ? 40 60 ns c l = 150pf t oed output driver enable delay ? 40 60 ns r l = 1k ? (3) , c l = 150pf t xcd cco output delay 0 20 40 ns c l = 150pf note: 1. timing is over recommended temperature and power supply voltages. 2. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 3. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . 12 commercial temperature range IDT728985 time slot interchange digital switch 256 x 256 figure 11. motorola non-multiplexed bus timing cs ds d0-d7 write 5708 drw14 r/ w a0-a5 d0-d7 read dta valid data valid data t css t rws t ads t csh t rwh t adh t dhr t dsw t swd t ddr t akd t dhw t akh $ ? symbol characteristics min. typ. (2) max. unit test conditions t css cs setup from ds rising 0 ?? ns t rws r/ w setup from ds rising 5 ?? ns t ads add setup from ds rising 5 ?? ns t csh cs hold after ds falling 0 ?? ns t rwh r/ w hold after ds falling 5 ?? ns t adh add hold after ds falling 5 ?? ns t ddr data setup from dta low on read 10 ?? ns c l = 150pf t dhr data hold on read 10 50 90 ns r l = 1k ? (3) , c l = 150pf t dsw data setup on write (fast write) 10 ?? ns t swd valid data delay on write (slow write) ?? 122 ns t dhw data hold on write 8 ?? ns t akd acknowledgment delay: c l = 150pf reading data memory ? 560 1220 ns reading/writing connection memory ? 300/370 730/800 ns writing to control register ? 40 70 ns reading to control register ? 40 70 ns t akh acknowledgment hold time 10 20 50 ns r l = 1k ? (3) , c l = 150pf note: 1. timing is over recommended temperature and power supply voltages. 2. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 3. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . 13 *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. and the st-bus ? is a trademark of mitel corp. corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: fif ohelp@idt.com www.idt.com* p pkg: www.idt.com/docs/psc4003.pdf j pkg: www.idt.com/docs/psc4008.pdf db pkg: www.idt.com/docs/psc4082.pdf 5708 drw15 xxxxxx idt device type x package process/ temperature range xx blank commercial (-40 c to +85 c) 728985 256 x 256 ? time slot interchange digital switch j plastic leaded chip carrier (plcc, j44-1) p db plastic dip (p40-1) plastic quad flatpack (pqfp, db44-1) 5/08/2000 pg. 1 6/05/2000 pgs. 1, 2, 12 and 13. 8/18/2000 pg. 2 01/24/2001 pgs. 1 and 8. 04/05/2001 pg. 10 |
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